1. Field of the Invention
The present invention relates to a field-effect transistor and, more specifically, to the configuration of a field-effect transistor that constitutes a logic circuit.
2. Description of the Related Art
The field-effect transistor is a very important semiconductor device in constructing an IC (integrated circuit). In particular, it is indispensable in an IC that constitutes a logic circuit.
On the other hand, in recent years, the technology of forming insulated-gate field-effect transistors that use a silicon thin film directly on an insulating substrate such as a glass substrate is now attracting much attention.
This technology enables direct formation on a glass substrate of field-effect transistors that constitute peripheral driver circuits for driving pixels as well as those for switching of the pixels in an active matrix liquid crystal display device, for instance. This greatly reduces the manufacturing cost compared to a case of using an externally provided IC chip.
Since the above type of driver circuits are required to operate at a high frequency with a basic frequency of several megahertz to tens of megahertz or more, they are constituted of field-effect transistors capable of high-speed operation in which the semiconductor layer is made of a polycrystalline silicon thin film or a single crystal silicon thin film each of which is high in crystallinity.
On the other hand, with the spread of portable information input/output equipment such as a notebook-sized personal computer, to enable long-term use of such equipment, it is now required that the power consumption be reduced in integrated circuits and a display device constituting such equipment.
Further, with the increase in the density of information handled, integrated circuits are also required to be improved in the degree of integration.
Among many factors of power consumption in an integrated circuit, power consumption in field-effect transistors that constitute the integrated circuit is not negligible.
In particular, where field-effect transistors are driven by using high-frequency signals of several megahertz or more, power consumption due to various parasitic capacitances becomes a serious problem.
FIG. 8 shows a sectional structure of a common thin-film field-effect transistor. Referring to FIG. 8, a silicon oxide film as an undercoat film 821 is formed on a substrate 820 having an insulating surface such as a glass substrate.
An island-like semiconductor region 801 is formed on the undercoat film 821. A gate electrode 805 is provided thereon through a gate insulating film 822. The portion of the island-like semiconductor region 801 under the gate electrode 805 is a channel forming region.
The portions of the island-like semiconductor region 801 on the left of and on the right of the gate electrode 805 are a source region 802 and a drain region 803, respectively, and are doped with an n-type impurity such as phosphorus. Thus, an n-channel thin-film transistor is formed. The channel forming region is disposed between the source region 802 and the drain region 803.
A source electrode 806 is electrically connected to the source region 802 via a contact hole 807 that is formed in an interlayer insulating film 823. A drain electrode 808 is electrically connected to the drain region 803 via a contact hole 809 that is formed in the interlayer insulating film 823.
The field-effect transistor shown in FIG. 8 has a structure called the planar structure in which all of the gate electrode, the source electrode, and the drain electrode are provided above the semiconductor in which the channel is formed. A structure in which all of the gate electrode, the source electrode, and the drain electrode are provided below the semiconductor in which the channel is formed is called the inverted planar structure.
In field-effect transistors structures such as the planar and inverted planar structures in which the gate electrode is relatively close to the source and drain electrodes, wiring parasitic capacitances Cw occur between the gate electrode and the source and drain electrodes.
Naturally, wiring parasitic capacitances also occur in field-effect transistors of structures called the staggered structure and the inverted staggered structure in which the channel forming semiconductor is interposed between the gate electrode and the source and drain electrodes. However, wiring parasitic capacitances more likely occur in planar and inverted planar field-effect transistors than in staggered and inverted staggered ones because of differences in structure.
Power consumption W [W] is expressed as W=(Cg+Cw)V.sup.2 f where Cw [F] is a wiring parasitic capacitance, Cg [F] is a gate input capacitance (in which the gate insulating film serves as a dielectric), f [Hz] is a frequency, and V [V] is a power supply voltage.
Therefore, in a field-effect transistor, the power consumption W increases as the voltage V or frequency f of an input signal that is applied between the gate electrode and the source or drain electrode increases.
It is difficult to reduce the gate input capacitance Cg because it is inherent to the structure itself of a field-effect transistor.
Therefore, to reduce the power consumption of a field-effect transistor in its driving, it would be effective to reduce wiring parasitic capacitances Cw between the gate electrode and the source and drain electrodes.
Since the capacitance is in inverse proportion to the distance between a pair of opposed electrodes, the wiring capacitances Cw may be reduced by increasing the distances between the gate electrode and the source and drain electrodes. Strictly speaking, the wiring capacitances Cw may be reduced by increasing the distances between the side end portion or face of the gate electrode and the gate-side side end portions or faces of the source and drain electrodes.
However, where field-effect transistors are arranged in integrated form, the size and the shape of a semiconductor region that constitutes each field-effect transistor is determined so as to maximize the degree of integration. Therefore, in many cases, the source and drain electrodes coextend with the source and drain regions (semiconductor) only in minimum areas necessary for obtaining electrical connections.
Therefore, if the positions of the source and drain electrodes are simply moved away from the gate electrode without changing the size of the semiconductor layer in which the source and drain regions are formed, there arises a possibility that electrical connections between the source and drain electrodes and the semiconductor layer become insufficient or even a connection failure occurs. Therefore, to increase the distances between the gate electrode and the source and drain electrodes, it is necessary to extend the source and drain regions (semiconductor layer) outward.
However, naturally the above measure increases the size of each device, obviously resulting in a reduction in the degree of integration.